In many applications, it is desirable to provide an event signal based on digital event time information. Digitally controlled DCDC converters are switched mode power supplies with a digital control loop. Besides the digital compensator (controller) the digital pulse width modulator is a core component of the control loop and acts as a digital-to-analog or more precisely as a digital-to-time converter which translates the digital duty cycle information into a pulse width modulated signal. It is usually implemented by a counter which is incremented/decremented in response to a digital clock signal. At the beginning of each switching period of the DCDC converter, the counter may be initialized with a start value. In each clock cycle during each clock switching period, the instantaneous counter value is compared to the digital control signal (or digital control value) provided by the compensator. When the counter value is equal to this control value, an event is triggered. In the specific example of the digital pulse width modulator, the pulse width modulation signal (PWM signal) is set either to high or to low. Usually, there are additional comparators which compare the counter value to other control signals and create other events. The sampling of the feedback analog-to-digital converter (ADC) is an example for such an additional event: a control value indicates the desired sampling point. When the counter (or counter value) is equal to this control signal (or control value), a sampling event is issued.
It is a trend in the design of switched mode power supplies (DCDC converters) to increase the switching frequency. It has been found that this often brings along that the clock frequency of the digital pulse width generator (DPWM generator) is increased, too. This means that the counter is incremented (or decremented) more often, and that each comparison is done more often. It has been found that a drawback is an increased power consumption of the digital control loop, which results in decreased DCDC converter efficiency. However, the latter is a key performance figure. For mobile products, the efficiency at low load currents is of particular importance. It has been found that, unfortunately, the efficiency decrease due to the digital control loop is visible especially at low load currents.
Accordingly, in some conventional digitally controlled DCDC converters, the switching frequency is relatively low. However, this brings along the drawbacks that there is a slow response to load and line jumps and there is also a slow response for dynamic voltage scaling. Also, such an architecture using a relatively low switching frequency is not feasible for high-speed converters, e.g. for envelope tracking. Moreover, DCDC converters with a relatively low switching frequency typically require large passive components.
In some other conventional DCDC converters, asynchronous or analog techniques are applied. For example, the counter is running with a reduced but constant frequency and a high resolution is achieved asynchronously by delay elements or multi-phase clocks. A drawback of such concepts is that many advantages of synchronous digital design, such as noise immunity, robustness, design automation, etc., get lost when these asynchronous techniques are used.
In view of this situation, there is a desire to have an energy efficient concept for a provision of an event signal with good accuracy. Also, there is a desire to have a digitally controlled energy converter with good efficiency even at comparatively high switching frequencies.